Thursday, September 19, 2019

Essays --

The CMOS technology plays a major role on the performance of microprocessors on very large scale integrated circuit chips. The rapid growth in CMOS technology with the shrinking transistor size towards 16nm has allowed for placement of several billions of transistors on a single microprocessor chip. This also leads to reduce the delay of logic gates in the order of pico seconds. One such method to improve the performance of microprocessor is to optimize the timing performance of dynamic circuits. In this paper a full adder circuit is designed and simulated using rate sensing keeper technique with L=0.12ÃŽ ¼m technology and VDD=1.2 V for improving the timing and noise tolerance also the noise tolerance characteristics of the full adder circuit designed using rate sensing keeper is compared with twin transistor based full adder circuit. Keywords— Bias,Domino logic, noise tolerance, rate sensing, timing optimization. I. INTRODUCTION HE rapid advancement in semiconductor technology with the shrinking transistor size towards 16nm has allowed for placement of several billion transistors on a single microprocessor chip[1]. CMOS technology plays a major role on the performance of VLSI microprocessors [2].The timing performance of the microprocessor can be improved by using dynamic circuits in microprocessors [3]. However the usage of dynamic circuits in microprocessors is limited due to many challenges including transistor sizing, charge sharing, leakage current, noise immunity and environmental and semiconductor process variations etc [4].Timing optimization of dynamic circuits can be achieved through several methods such as transistor sizing, using multiple threshold voltages etc.[5],[6],[7].The aggressive scaling of transistors and interc... ... and the experimental results shows that the full adder circuit designed using rate sensing keeper transistor technique gives superior performance compared to the other alternatives such as Conditional Keeper (CKP) and current mirror-based keeper (LCR). Fig.22. Output noise Vs Vbias characteristics of full adder using Rate Sensing Keeper technique IV. CONCLUSION In this paper the performance of a full adder circuit designed using rate sensing keeper transistor technique is analyzed in detail and its performance is compared with other full adder circuits. The full adder circuit is simulated using L=0.12ÃŽ ¼m technology along with supply voltage VDD=1.2V. The experimental results shows that the full adder circuit designed using rate sensing keeper transistor technique gives superior performance compared to full adder circuits designed using conventional domino techniques.

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